MCP2030A-I/P【PDF 50/66 页】IC KEYLESS ENTRY AFE 3CH 14PDIP

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MCP2030

CS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

SCLK

SDIO

MSb

LSb

Command

Address

Data Byte

Row

Parity Bit

FIGURE 5-12:

Detailed SPI Timing (AFE).

5.31.2.1

Clamp On Command

5.31.2.5

AGC Preserve On Command

This command results in activating (turning on) the

modulation transistors of all enabled channels; channels

enabled in Configuration Register 0 (Register 5-1).

This command results in preserving the AGC level

during each AGC initialization time and apply the value

to the data slicing circuit for the following data stream.

The preserved AGC value is reset by a Soft Reset, and

5.31.2.2

Clamp Off Command

a new AGC value is acquired and preserved when it

This command results in deactivating (turning off) the

modulation transistors of all channels.

5.31.2.3 Sleep Command

This command places the device in Sleep mode –

minimizing current draw by disabling all but the

essential circuitry. Any other command wakes the

device from Sleep (e.g., Clamp Off command).

starts a new AGC initialization time. This feature is

disabled by an AGC Preserve Off command (see

Section 5.19 “AGC Preserve” ).

5.31.2.6 AGC Preserve Off Command

This command disables the AGC preserve feature and

returns to the normal AGC tracking mode, fast tracking

during AGC settling time and slow tracking after that

(see Section 5.19 “AGC Preserve” ).

5.31.2.4 Soft Reset Command

The device issues a Soft Reset when it receives an

external Soft Reset command. The external Soft Reset

5.31.3

READ/WRITE COMMANDS FOR

CONFIGURATION REGISTERS

command is typically used to end a SPI communication

sequence or to initialize the device for the next signal

detection sequence, etc. See Section 5.20 “Soft

Reset” for more details on Soft Reset.

If a Soft Reset command is sent during a “Clamp-on”

condition, the device still keeps the “Clamp-on” condi-

tion after the Soft Reset execution. The Soft Reset is

executed in Active mode only, not in Standby mode.

The SPI Soft Reset command is ignored if the device is

not in Active mode.

DS21981A-page 50

The device includes 8 Configuration registers, includ-

ing a Column Parity register and STATUS register. All

registers are readable and writable via SPI, except the

STATUS register, which is read-only. Bit 0 of each

register is a row parity bit (except for STATUS Register

7) that makes the register contents an odd number.

? 2005 Microchip Technology Inc.

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